Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date         : Sun Apr 12 14:21:53 2026
| Host         : debian running 64-bit Debian GNU/Linux 13 (trixie)
| Command      : report_control_sets -verbose -file system_wrapper_control_sets_placed.rpt
| Design       : system_wrapper
| Device       : xc7z020
-------------------------------------------------------------------------------------------

Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |   468 |
|    Minimum number of control sets                        |   468 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |   240 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |   468 |
| >= 0 to < 4        |     2 |
| >= 4 to < 6        |     5 |
| >= 6 to < 8        |    14 |
| >= 8 to < 10       |    29 |
| >= 10 to < 12      |     1 |
| >= 12 to < 14      |     4 |
| >= 14 to < 16      |     0 |
| >= 16              |   413 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |             226 |           73 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |            2485 |          667 |
| Yes          | No                    | No                     |            5614 |         1209 |
| Yes          | No                    | Yes                    |               0 |            0 |
| Yes          | Yes                   | No                     |            3299 |          849 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+-------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
|          Clock Signal         |                                                                                                                           Enable Signal                                                                                                                          |                                                                                              Set/Reset Signal                                                                                             | Slice Load Count | Bel Load Count | Bels / Slice |
+-------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full                                                                                                                                     | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[26].i_mem/g_individual.i_mem_a/gen_dram.gen_rom.d_out[18]_i_1_n_0                 |                1 |              3 |         3.00 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/writer_0/inst/fifo_0/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i                                                                                                                                  |                2 |              3 |         1.50 |
|  system_i/pll_0/inst/clk_out1 | system_i/writer_0/inst/buf_1/E[0]                                                                                                                                                                                                                                | system_i/writer_0/inst/fifo_0_i_1_n_0                                                                                                                                                                     |                1 |              4 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_4/int_rready_wire                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_1/int_data_reg_reg[25]_0                                                                                                                                                    |                2 |              4 |         2.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_3/buf_1/E[0]                                                                                                                                                                                                                             | system_i/hub_0/inst/buf_3/buf_1/SR[0]                                                                                                                                                                     |                2 |              4 |         2.00 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/writer_0/inst/fifo_0/xpm_fifo_base_inst/xpm_fifo_rst_inst/SR[0]                                                                                                                                  |                2 |              5 |         2.50 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/rst_0/U0/EXT_LPF/lpf_int                                                                                                                                                                         |                2 |              5 |         2.50 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.i_cntrl_wrap_buff_re/sclr_count_0                                                                                                                               | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/sclr_int                                                                                                                          |                2 |              6 |         3.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/rst_0/U0/SEQ/seq_cnt_en                                                                                                                                                                                                                                 | system_i/rst_0/U0/SEQ/SEQ_COUNTER/q_int[5]_i_1_n_0                                                                                                                                                        |                2 |              6 |         3.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.i_latch_op/sclr_count                                                                                                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/sclr_int                                                                                                                          |                2 |              6 |         3.00 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/writer_0/inst/fifo_0/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0]                                                                                                                                   |                4 |              6 |         1.50 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_1/U0/i_synth/decimator.decimation_filter/int/gen_stages[5].gen_unfolded.int_comb_stage/gen_nd_out_dly/gen_rtl.gen_dly.gen_regs.delay_bus_reg[1]_0                                                                                                   | system_i/cic_1/U0/i_synth/decimator.decimation_filter/int/gen_stages[5].gen_unfolded.int_comb_stage/gen_nd_out_dly/SR[0]                                                                                  |                2 |              7 |         3.50 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_0/U0/i_synth/decimator.decimation_filter/rate_we_i                                                                                                                                                                                                  | system_i/cic_0/U0/i_synth/reset                                                                                                                                                                           |                2 |              7 |         3.50 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_1/U0/i_synth/decimator.decimation_filter/rate_we_i                                                                                                                                                                                                  | system_i/cic_1/U0/i_synth/reset                                                                                                                                                                           |                2 |              7 |         3.50 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_0/U0/i_synth/decimator.decimation_filter/int/gen_stages[5].gen_unfolded.int_comb_stage/gen_nd_out_dly/gen_rtl.gen_dly.gen_regs.delay_bus_reg[1]_0                                                                                                   | system_i/cic_0/U0/i_synth/decimator.decimation_filter/int/gen_stages[5].gen_unfolded.int_comb_stage/gen_nd_out_dly/SR[0]                                                                                  |                2 |              7 |         3.50 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_2/U0/i_synth/decimator.decimation_filter/int/gen_stages[5].gen_unfolded.int_comb_stage/gen_nd_out_dly/gen_rtl.gen_dly.gen_regs.delay_bus_reg[1]_0                                                                                                   | system_i/cic_2/U0/i_synth/decimator.decimation_filter/int/gen_stages[5].gen_unfolded.int_comb_stage/gen_nd_out_dly/SR[0]                                                                                  |                3 |              7 |         2.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_2/U0/i_synth/decimator.decimation_filter/rate_we_i                                                                                                                                                                                                  | system_i/cic_2/U0/i_synth/reset                                                                                                                                                                           |                2 |              7 |         3.50 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_3/U0/i_synth/decimator.decimation_filter/int/gen_stages[5].gen_unfolded.int_comb_stage/gen_nd_out_dly/gen_rtl.gen_dly.gen_regs.delay_bus_reg[1]_0                                                                                                   | system_i/cic_3/U0/i_synth/decimator.decimation_filter/int/gen_stages[5].gen_unfolded.int_comb_stage/gen_nd_out_dly/SR[0]                                                                                  |                2 |              7 |         3.50 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_3/U0/i_synth/decimator.decimation_filter/enable_dly0                                                                                                                                                                                                | system_i/cic_3/U0/i_synth/reset                                                                                                                                                                           |                2 |              7 |         3.50 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_3/U0/i_synth/decimator.decimation_filter/rate_we_i                                                                                                                                                                                                  | system_i/cic_3/U0/i_synth/reset                                                                                                                                                                           |                2 |              7 |         3.50 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_2/U0/i_synth/decimator.decimation_filter/enable_dly0                                                                                                                                                                                                | system_i/cic_2/U0/i_synth/reset                                                                                                                                                                           |                2 |              7 |         3.50 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE061_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                4 |              8 |         2.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE054_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                4 |              8 |         2.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE029_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                2 |              8 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE052_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                3 |              8 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE050_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                2 |              8 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE047_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                2 |              8 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE045_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                3 |              8 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE043_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                3 |              8 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE041_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                1 |              8 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE027_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                4 |              8 |         2.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE038_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                3 |              8 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE032_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                1 |              8 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE025_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                3 |              8 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE056_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                3 |              8 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE0                                                                                                                                                                                                                              | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                2 |              8 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/int_data_reg_reg[33]_0                                                                                                                                                                                                           | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                2 |              8 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE074_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                3 |              8 |         2.67 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                4 |              8 |         2.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE036_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                2 |              8 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE016_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                3 |              8 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE019_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                2 |              8 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE023_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                1 |              8 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE072_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                2 |              8 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE070_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                5 |              8 |         1.60 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE068_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                2 |              8 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE065_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                3 |              8 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE063_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                5 |              8 |         1.60 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE034_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                3 |              8 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_1/CE059_out                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N                                                                                                                                       |                2 |              8 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full                                                                                                                                     | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[24].i_mem/g_individual.i_mem_a/gen_dram.gen_rom.d_out[23]_i_1_n_0                 |                3 |             11 |         3.67 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.i_cntrl_wrap_buff_re/Q[0]                                                                                |                7 |             12 |         1.71 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_2/E[0]                                                                                                                                                                                                                                   |                                                                                                                                                                                                           |                2 |             12 |         6.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_0/U0/i_synth/decimator.decimation_filter/enable_dly0                                                                                                                                                                                                | system_i/cic_0/U0/i_synth/reset                                                                                                                                                                           |                3 |             13 |         4.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_1/U0/i_synth/decimator.decimation_filter/enable_dly0                                                                                                                                                                                                | system_i/cic_1/U0/i_synth/reset                                                                                                                                                                           |                5 |             13 |         2.60 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[13].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[12].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[12].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[13].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[13].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[13].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[13].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[13].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[13].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[13].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[11].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[12].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[12].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[12].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[12].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[12].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[12].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[11].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[11].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[11].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[11].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[6].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__30_n_0  |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[16].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[16].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[16].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[16].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[16].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[16].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[15].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[15].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[14].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[15].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[14].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[14].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[14].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[14].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[14].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[14].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[14].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[3].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__27_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[3].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[8].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__32_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[8].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[8].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__32_n_0  |                                                                                                                                                                                                           |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__31_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__31_n_0  |                                                                                                                                                                                                           |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[6].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__30_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[6].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[4].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[5].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__29_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[5].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[5].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__29_n_0  |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[4].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__28_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[4].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[4].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__28_n_0  |                                                                                                                                                                                                           |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[9].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__33_n_0  |                                                                                                                                                                                                           |                6 |             16 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[3].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__27_n_0  |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[2].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__26_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[2].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                6 |             16 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[2].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__26_n_0  |                                                                                                                                                                                                           |                6 |             16 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[1].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__25_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[1].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[1].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__25_n_0  |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[16].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__40_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[16].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[16].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__40_n_0 |                                                                                                                                                                                                           |                6 |             16 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[15].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__39_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[15].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[15].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__39_n_0 |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[14].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__38_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[14].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[1].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[11].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[11].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[2].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[2].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[1].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[1].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[1].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[1].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[1].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[1].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[11].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[1].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[0].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[0].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[0].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[0].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[0].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[0].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[0].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[0].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[9].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__33_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[9].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[9].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[9].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[8].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[8].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[8].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[8].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[8].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[8].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[8].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[8].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[9].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[7].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[7].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[7].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[7].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[6].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[6].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[6].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[10].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_mem_allign/E[0]                                                                               | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_old_data_clred_dly/SR[0]               |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_mem_allign/E[0]                                                                               | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_old_data_clred_dly/SR[0]               |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_mem_allign/E[0]                                                                               | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_old_data_clred_dly/SR[0]               |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_mem_allign/E[0]                                                                               | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_old_data_clred_dly/SR[0]               |                6 |             16 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full                                                                                                                                     | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[0].i_mem/g_individual.i_mem_a/d_out0                                              |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full                                                                                                                                     | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[0].i_mem/g_individual.i_mem_a/d_out0                                              |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full                                                                                                                                     | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[0].i_mem/g_individual.i_mem_a/d_out0                                              |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full                                                                                                                                     | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[0].i_mem/g_individual.i_mem_a/d_out0                                              |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[10].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[10].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[6].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[10].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[10].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[10].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[10].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[10].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[9].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[9].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[9].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[9].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[9].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[2].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[3].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[3].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[3].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[3].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[3].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[3].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[2].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[2].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[2].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[2].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[3].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[2].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[17].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[17].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[17].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[17].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[17].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[17].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[17].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[17].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[16].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                             |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[5].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[6].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[6].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[6].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[6].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[5].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[5].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[5].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[5].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[5].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[5].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[16].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                     |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[5].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[4].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[4].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[4].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[5].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__12_n_0  |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[4].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[4].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[4].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[4].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.mem_reg[7]0                                                                              |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[3].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7]0                                                                      |                                                                                                                                                                                                           |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[12].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__36_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[12].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__31_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__30_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__29_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__28_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__27_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__26_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__25_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[16].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__40_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[16].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[15].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__39_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[15].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[14].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__38_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[14].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[13].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__37_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[13].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__32_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[11].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__35_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[11].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[10].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__34_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[10].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__24_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[9].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__16_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[9].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__15_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__14_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__13_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__12_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__11_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__10_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[13].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__45_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[13].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__63_n_0  |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__64_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__64_n_0  |                                                                                                                                                                                                           |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__65_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__65_n_0  |                                                                                                                                                                                                           |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[16].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__42_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[16].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[16].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__42_n_0 |                                                                                                                                                                                                           |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[15].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__43_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[15].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[15].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__43_n_0 |                                                                                                                                                                                                           |                6 |             16 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[14].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__44_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[14].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[14].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__44_n_0 |                                                                                                                                                                                                           |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__9_n_0                                                             | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[13].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__45_n_0 |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[12].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__46_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[12].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[12].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__46_n_0 |                                                                                                                                                                                                           |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[11].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__47_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[11].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[11].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__47_n_0 |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[10].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__48_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[10].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[10].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__48_n_0 |                                                                                                                                                                                                           |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__66_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__66_n_0  |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[9].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__33_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[9].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__65_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[11].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__1_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[11].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[10].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__0_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[10].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__56_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[9].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__57_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[9].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__58_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__59_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__60_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__61_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__62_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__63_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__64_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[12].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__2_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[12].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[16].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__42_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[16].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[15].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__43_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[15].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[14].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__44_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[14].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[13].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__45_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[13].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[12].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__46_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[12].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[11].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__47_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[11].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[10].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__48_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[10].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__66_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_4/int_rready_wire                                                                                                                                                                                                                        | system_i/hub_0/inst/buf_3/buf_1/int_valid_reg_reg_0                                                                                                                                                       |                7 |             16 |         2.29 |
|  system_i/pll_0/inst/clk_out1 | system_i/writer_0/inst/buf_0/E[0]                                                                                                                                                                                                                                | system_i/writer_0/inst/buf_0/SR[0]                                                                                                                                                                        |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__49_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__8_n_0                                                             | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[16].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__23_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[16].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[15].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__22_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[15].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[14].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__21_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[14].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[13].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__20_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[13].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[12].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__19_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[12].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[11].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__18_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[11].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[10].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__17_n_0                                                           | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[10].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__7_n_0                                                             | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[0].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[9].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2_n_0                                                                | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[9].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__41_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[8].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[13].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__37_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[13].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__50_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[6].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__51_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__52_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[4].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__53_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[3].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__54_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[2].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__55_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[1].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                          |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[16].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__6_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[16].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[15].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__5_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[15].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[14].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__4_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[14].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[13].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg[15]_i_2__3_n_0                                                            | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[13].g_data.i_data_casc_dly/g_buff.i_buff/sclr_int                         |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[13].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__20_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[13].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[3].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__10_n_0  |                                                                                                                                                                                                           |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[2].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__9_n_0   | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[2].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[2].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__9_n_0   |                                                                                                                                                                                                           |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[1].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__8_n_0   | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[1].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[1].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__8_n_0   |                                                                                                                                                                                                           |                6 |             16 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[16].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__23_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[16].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[16].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__23_n_0 |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[15].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__22_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[15].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[15].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__22_n_0 |                                                                                                                                                                                                           |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[14].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__21_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[14].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                6 |             16 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[14].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__21_n_0 |                                                                                                                                                                                                           |                6 |             16 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[3].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__10_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[3].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[13].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__20_n_0 |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[12].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__19_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[12].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[12].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__19_n_0 |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[11].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__18_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[11].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[11].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__18_n_0 |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[10].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__17_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[10].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[10].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__17_n_0 |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[0].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__7_n_0   | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[0].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[0].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__7_n_0   |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[9].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1_n_0      | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[9].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[9].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__16_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[9].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[14].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__38_n_0 |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[13].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__37_n_0 |                                                                                                                                                                                                           |                6 |             16 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[12].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__36_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[12].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[12].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__36_n_0 |                                                                                                                                                                                                           |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[11].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__35_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[11].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[11].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__35_n_0 |                                                                                                                                                                                                           |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[10].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__34_n_0 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[10].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                6 |             16 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[10].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__34_n_0 |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[0].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__24_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[0].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[0].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__24_n_0  |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__62_n_0  |                                                                                                                                                                                                           |                7 |             16 |         2.29 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[9].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__16_n_0  |                                                                                                                                                                                                           |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[8].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__15_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[8].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[8].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__15_n_0  |                                                                                                                                                                                                           |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__14_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__14_n_0  |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[6].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__13_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[6].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[6].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__13_n_0  |                                                                                                                                                                                                           |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[5].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__12_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[5].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[4].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__11_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[4].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[4].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__11_n_0  |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[9].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__57_n_0  |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[13].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__3_n_0  |                                                                                                                                                                                                           |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[12].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__2_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[12].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[9].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1_n_0      |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[12].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__2_n_0  |                                                                                                                                                                                                           |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[11].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__1_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[11].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[11].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__1_n_0  |                                                                                                                                                                                                           |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[10].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__0_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[10].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[10].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__0_n_0  |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[0].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__56_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[0].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[0].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__56_n_0  |                                                                                                                                                                                                           |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[9].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__57_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[9].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[8].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__41_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[8].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[8].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__58_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[8].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[8].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__58_n_0  |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__59_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__59_n_0  |                                                                                                                                                                                                           |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__60_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                2 |             16 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[6].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__60_n_0  |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__61_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[5].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__61_n_0  |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__63_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[3].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__62_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[4].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[14].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__4_n_0  |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[8].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__41_n_0  |                                                                                                                                                                                                           |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__49_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__49_n_0  |                                                                                                                                                                                                           |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[6].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__50_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[6].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[6].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__50_n_0  |                                                                                                                                                                                                           |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[5].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__51_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[5].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[5].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__51_n_0  |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[4].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__52_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[4].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[4].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__52_n_0  |                                                                                                                                                                                                           |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[3].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__53_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[3].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[3].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__53_n_0  |                                                                                                                                                                                                           |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[2].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__54_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[2].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[2].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__54_n_0  |                                                                                                                                                                                                           |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[1].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__55_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[1].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int  |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[1].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__55_n_0  |                                                                                                                                                                                                           |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[16].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__6_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[16].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[16].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__6_n_0  |                                                                                                                                                                                                           |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[15].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__5_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[15].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                5 |             16 |         3.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[15].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__5_n_0  |                                                                                                                                                                                                           |                6 |             16 |         2.67 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[14].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__4_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[14].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                3 |             16 |         5.33 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[13].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus[0][15]_i_1__3_n_0  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[13].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/sclr_int |                4 |             16 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/writer_0/inst/fifo_0/xpm_fifo_base_inst/rdp_inst/FSM_onehot_gen_fwft.curr_fwft_state_reg[3]                                                                                                                                                             | system_i/writer_0/inst/fifo_0/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0]                                                                                                                                   |                6 |             17 |         2.83 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/rate_0/inst/p_0_in                                                                                                                                                                               |                4 |             17 |         4.25 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/rate_1/inst/p_0_in                                                                                                                                                                               |                5 |             17 |         3.40 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/rate_2/inst/p_0_in                                                                                                                                                                               |                6 |             17 |         2.83 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/rate_3/inst/p_0_in                                                                                                                                                                               |                5 |             17 |         3.40 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_1/buf_1/E[0]                                                                                                                                                                                                                             |                                                                                                                                                                                                           |                7 |             19 |         2.71 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_0/buf_0/int_ready_reg_reg_0                                                                                                                                                                                                              |                                                                                                                                                                                                           |                4 |             19 |         4.75 |
|  system_i/pll_0/inst/clk_out1 | system_i/writer_0/inst/fifo_0/xpm_fifo_base_inst/xpm_fifo_rst_inst/ram_wr_en_i                                                                                                                                                                                   | system_i/writer_0/inst/fifo_0/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0]                                                                                                                                   |                7 |             19 |         2.71 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full                                                                                                                                     | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[18].i_mem/g_individual.g_mem_b.i_mem_b/gen_dram.gen_rom.d_out[23]_i_1_n_0         |                5 |             20 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_3/buf_0/int_ready_reg_reg_0                                                                                                                                                                                                              |                                                                                                                                                                                                           |                7 |             23 |         3.29 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_3/buf_1/int_ready_wire                                                                                                                                                                                                                   |                                                                                                                                                                                                           |                7 |             23 |         3.29 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_0/U0/i_synth/decimator.decimation_filter/rfd_int_reg_n_0                                                                                                                                                                                            | system_i/cic_0/U0/i_synth/reset                                                                                                                                                                           |                8 |             24 |         3.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_1/U0/i_synth/decimator.decimation_filter/rfd_int_reg_n_0                                                                                                                                                                                            | system_i/cic_1/U0/i_synth/reset                                                                                                                                                                           |                6 |             24 |         4.00 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/sclr_int                                                                                                                          |               11 |             25 |         2.27 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/cic_2/U0/i_synth/decimator.decimation_filter/sclr_int                                                                                                                                            |                5 |             26 |         5.20 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/cic_3/U0/i_synth/decimator.decimation_filter/sclr_int                                                                                                                                            |                5 |             26 |         5.20 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/dac_0/inst/int_rst_reg[0]_i_1_n_0                                                                                                                                                                |               17 |             28 |         1.65 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_4/int_rready_wire                                                                                                                                                                                                                        |                                                                                                                                                                                                           |                9 |             31 |         3.44 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.i_latch_op/wr_enable                                                                                                                                            |                                                                                                                                                                                                           |                4 |             32 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_0/U0/i_synth/decimator.decimation_filter/comb/gen_stages[1].gen_folded.int_comb_stage/gen_nd_out_dly/E[0]                                                                                                                                           | system_i/cic_0/U0/i_synth/decimator.decimation_filter/RDY0                                                                                                                                                |               11 |             32 |         2.91 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/we_ce                                                                               |                                                                                                                                                                                                           |                4 |             32 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_1/U0/i_synth/decimator.decimation_filter/comb/gen_stages[1].gen_folded.int_comb_stage/gen_nd_out_dly/E[0]                                                                                                                                           | system_i/cic_1/U0/i_synth/decimator.decimation_filter/RDY0                                                                                                                                                |                8 |             32 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/rd_enable                                                                                                                                    |                                                                                                                                                                                                           |                4 |             32 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/writer_0/inst/buf_0/int_awready_wire                                                                                                                                                                                                                    |                                                                                                                                                                                                           |                8 |             32 |         4.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/we_ce                                                                               |                                                                                                                                                                                                           |                4 |             32 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/we_ce                                                                               |                                                                                                                                                                                                           |                4 |             32 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/we_ce                                                                               |                                                                                                                                                                                                           |                4 |             32 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full                                                                                                                                     | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.i_cntrl_wrap_buff_re/Q[0]                                                                                |               14 |             33 |         2.36 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_0/U0/i_synth/decimator.decimation_filter/comb/gen_stages[1].gen_folded.int_comb_stage/gen_split_accum[0].gen_comb_mem_src.gen_en_dly/en_dly                                                                                                         | system_i/cic_0/U0/i_synth/decimator.decimation_filter/sclr_int                                                                                                                                            |               13 |             36 |         2.77 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_0/U0/i_synth/decimator.decimation_filter/comb/gen_stages[1].gen_folded.int_comb_stage/gen_split_accum[0].gen_comb_mem_src.gen_en_dly/en_dly                                                                                                         |                                                                                                                                                                                                           |                5 |             36 |         7.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_1/U0/i_synth/decimator.decimation_filter/comb/gen_stages[1].gen_folded.int_comb_stage/gen_split_accum[0].gen_comb_mem_src.gen_en_dly/en_dly                                                                                                         |                                                                                                                                                                                                           |                5 |             36 |         7.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_1/U0/i_synth/decimator.decimation_filter/comb/gen_stages[1].gen_folded.int_comb_stage/gen_split_accum[0].gen_comb_mem_src.gen_en_dly/en_dly                                                                                                         | system_i/cic_1/U0/i_synth/decimator.decimation_filter/sclr_int                                                                                                                                            |               20 |             36 |         1.80 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_0/U0/i_synth/decimator.decimation_filter/comb/gen_stages[1].gen_folded.int_comb_stage/gen_split_accum[0].gen_comb_mem_src.gen_en_dly/E[0]                                                                                                           | system_i/cic_0/U0/i_synth/decimator.decimation_filter/sclr_int                                                                                                                                            |                5 |             36 |         7.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_1/U0/i_synth/decimator.decimation_filter/comb/gen_stages[1].gen_folded.int_comb_stage/gen_split_accum[0].gen_comb_mem_src.gen_en_dly/E[0]                                                                                                           | system_i/cic_1/U0/i_synth/decimator.decimation_filter/sclr_int                                                                                                                                            |                5 |             36 |         7.20 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_1/buf_0/int_ready_reg_reg_0                                                                                                                                                                                                              |                                                                                                                                                                                                           |               11 |             37 |         3.36 |
|  system_i/pll_0/inst/clk_out1 | system_i/hub_0/inst/buf_2/PS7_i[0]                                                                                                                                                                                                                               |                                                                                                                                                                                                           |               12 |             37 |         3.08 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_1/U0/i_synth/decimator.decimation_filter/comb/gen_stages[0].gen_folded.int_comb_stage/gen_split_accum[0].gen_comb_mem_src.gen_en_dly/en_dly                                                                                                         |                                                                                                                                                                                                           |                5 |             39 |         7.80 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_1/U0/i_synth/decimator.decimation_filter/comb/gen_stages[0].gen_folded.int_comb_stage/gen_split_accum[0].gen_comb_mem_src.gen_en_dly/en_dly                                                                                                         | system_i/cic_1/U0/i_synth/decimator.decimation_filter/sclr_int                                                                                                                                            |               18 |             39 |         2.17 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_0/U0/i_synth/decimator.decimation_filter/comb/gen_stages[0].gen_folded.int_comb_stage/gen_split_accum[0].gen_comb_mem_src.gen_en_dly/E[0]                                                                                                           | system_i/cic_0/U0/i_synth/decimator.decimation_filter/sclr_int                                                                                                                                            |                5 |             39 |         7.80 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_0/U0/i_synth/decimator.decimation_filter/comb/gen_stages[0].gen_folded.int_comb_stage/gen_split_accum[0].gen_comb_mem_src.gen_en_dly/en_dly                                                                                                         | system_i/cic_0/U0/i_synth/decimator.decimation_filter/sclr_int                                                                                                                                            |               15 |             39 |         2.60 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_0/U0/i_synth/decimator.decimation_filter/comb/gen_stages[0].gen_folded.int_comb_stage/gen_split_accum[0].gen_comb_mem_src.gen_en_dly/en_dly                                                                                                         |                                                                                                                                                                                                           |                5 |             39 |         7.80 |
|  system_i/pll_0/inst/clk_out1 | system_i/cic_1/U0/i_synth/decimator.decimation_filter/comb/gen_stages[0].gen_folded.int_comb_stage/gen_split_accum[0].gen_comb_mem_src.gen_en_dly/E[0]                                                                                                           | system_i/cic_1/U0/i_synth/decimator.decimation_filter/sclr_int                                                                                                                                            |                5 |             39 |         7.80 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_s_data_chan_fifo.i_s_data_chan_fifo/rfd_int_ce                                                                                                                                         |                                                                                                                                                                                                           |                8 |             64 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_s_data_chan_fifo.i_s_data_chan_fifo/wr_enable                                                                                                                                          |                                                                                                                                                                                                           |                8 |             64 |         8.00 |
|  system_i/pll_0/inst/clk_out1 | system_i/writer_0/inst/buf_1/int_wready_wire                                                                                                                                                                                                                     |                                                                                                                                                                                                           |               16 |             65 |         4.06 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/dds_2/inst/int_cntr_reg[31]_i_1_n_0                                                                                                                                                              |               20 |             73 |         3.65 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/dds_3/inst/int_cntr_reg[31]_i_1_n_0                                                                                                                                                              |               26 |             73 |         2.81 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/dds_0/inst/int_cntr_reg[31]_i_1_n_0                                                                                                                                                              |               31 |             97 |         3.13 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full                                                                                                                                     | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/sclr_int                                                                                                                          |               41 |             98 |         2.39 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/cic_1/U0/i_synth/reset                                                                                                                                                                           |               42 |            105 |         2.50 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/cic_0/U0/i_synth/reset                                                                                                                                                                           |               37 |            105 |         2.84 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  |                                                                                                                                                                                                           |               74 |            305 |         4.12 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/cic_1/U0/i_synth/decimator.decimation_filter/sclr_int                                                                                                                                            |              223 |            910 |         4.08 |
|  system_i/pll_0/inst/clk_out1 |                                                                                                                                                                                                                                                                  | system_i/cic_0/U0/i_synth/decimator.decimation_filter/sclr_int                                                                                                                                            |              209 |            910 |         4.35 |
|  system_i/pll_0/inst/clk_out1 | system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full                                                                                                                                     |                                                                                                                                                                                                           |              832 |           4147 |         4.98 |
+-------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+


